module top (
    input clk,
    input rst_n,
    output tx_data,
    output tx_valid,
    input rx_data,
    input rx_valid,
    output real_output
);

// Some instances with normal connections
submodule_a u_sub_a (
    .clk(clk),
    .rst_n(rst_n),
    .data_out(tx_data),
    .valid_out(tx_valid)
);

// Instance that might cause "wire" parsing issue
test_module u_test (
    .clk(clk),
    .rst_n(rst_n),
    .wire_port(real_output),  // This connects wire_port to a real signal
    .normal_port(rx_valid)
);

endmodule

module submodule_a (
    input clk,
    input rst_n,
    output data_out,
    output valid_out
);

assign data_out = 1'b0;
assign valid_out = 1'b0;

endmodule

module test_module (
    input clk,
    input rst_n,
    output wire_port,
    output normal_port
);

assign wire_port = 1'b1;
assign normal_port = 1'b1;

endmodule